module cordic_control_unit
#(
  parameter DATA_WIDTH = 16,
  parameter COUNT_SIZE = 4
)(
  //OUTPUTS
  output reg reg_en,
  output reg count_en,
  output reg reg_src,
  output reg count_clear,
  //INPUTS
  input start,
  input [COUNT_SIZE - 1:0] count,
  input clk,
  input rst_n
);

//=============================================================================
// 1)  X, Y and TETA registers: Mux source
//=============================================================================
localparam CORE  = 1'b0;
localparam INPUT = 1'b1;

//=============================================================================
// 2)  X, Y, TETA and counter enable
//=============================================================================
localparam DISABLE = 1'b0;
localparam ENABLE  = 1'b1;

//=============================================================================
// 3)  FSM STATES
//=============================================================================
localparam IDLE       = 1'b0;
localparam PROCESSING = 1'b1;

reg state, next_state;

//State Memory
always @(posedge clk, negedge rst_n)
  begin
    if(!rst_n)
      state <= IDLE;
    else
      state <= next_state;
  end

//Next State Logic
always @(*)
  begin
    next_state = state;
    case(state)
      IDLE:       next_state = (start) ? PROCESSING : IDLE;
      PROCESSING: next_state = (count == {COUNT_SIZE{1'b1}}) ? IDLE : PROCESSING;
      default:    next_state = IDLE;
    endcase
  end

//Output Logic  
always @(*)
  begin
    reg_en      = DISABLE;
    count_en    = DISABLE;
    reg_src     = INPUT;
    count_clear = ENABLE;
    case(state)
      IDLE:
        begin
          reg_en      = DISABLE;
          count_en    = DISABLE;
          reg_src     = INPUT;
          count_clear = ENABLE;
        end
      PROCESSING:
        begin
          reg_en      = ENABLE;
          count_en    = ENABLE;
          reg_src     = CORE;
          count_clear = DISABLE;
        end
    endcase
  end

endmodule
